The present invention relates to a semiconductor memory device, and particularly to the control of a clearing operation in a static random access memory (SRAM) device.
The capacity of a typical semiconductor memory has recently been increased to such an extent that the memory can be used in an image processing device. However, various new functions are required for the memory, so that it can be more advantageously applied to image processors. Such functions include, for example, the instantaneous clearing of the stored data, whereby data stored in some or all of the memory cells in the memory is cleared and "0" or "1" data is written in the cleared memory cells.
In a conventional general-purpose SRAM, reading or writing of data can be performed for only a memory cell of an address designated by an address signal. Therefore, when data stored in all the memory cells in the memory device is to be cleared, it is necessary to sequentially designate all the addresses while successively writing the data "0" or "1" in each memory cell.
Consequently, the same number of writing operations have to be performed as the number of bits to be cleared. With a 256 k bit SRAM comprising 32 k words.times.8 bits, for example, a processing time of about 3 ms (100 ns.times.32.times.1024) is required, with a required minimum writing time of 100 ns.
However, since such a long clearing process time is highly undesirable when the memory is incorporated in an image processing device in which high-speed operating characteristics are required, it is necessary, therefore, that the clearing process time be as short as possible.
Another disadvantage of the prior art memory is that during the clearing process, the same quantity of current as is flowing during the writing mode, flows through the bit lines and memory cells. Consequently, a large amount of power is consumed, and this should be avoided.
More explicitly, as is shown in FIG. 1, which shows an SRAM known in this field, current i.sub.3, which is the sum of current i.sub.1 and current i.sub.2, flows during the clearing operation, where current i.sub.1 denotes a current flowing through a power node of V.sub.DD potential, - load transistor T.sub.21 on the bit line - bit line BL, a - memory cell MC (transistor T.sub.23 for a transfer gate and - drive transistor T.sub.25) and the - V.sub.SS potential, and current i.sub.2 denotes a current flowing through the V.sub.DD potential power node, - load transistor T.sub.21 on the bit line, - bit line BL, a - data write circuit (write transistor T.sub.27 and - write data line DL, and the - V.sub.SS potential. Current i.sub.3 normally amounts to about 1 milliampere per column. With a 256 k bit SRAM having 512 columns, for example, DC current as high as several ten milliamperes flows therethrough during the write operation. Accordingly, a significant reduction in power consumption is urgently required.